IBM AT and AT compatible personal computers use an AT standardized bus system for internal communication. The AT bus is generally called Industry Standard Architecture (ISA) bus for 8 and 16 bit systems and Extended Industry Standard Architecture (EISA) for 32 bit systems. The requirements of the AT bus are described in detail in AT Bus Design, Edward Solari (Annabooks, 1990), the subject matter of which is incorporated herein by reference. The AT bus is an interface between various functional units of the computer, e.g., the central processing unit (CPU) memory and various interfaces for input/output (I/O) devices. The AT bus provides the logic necessary to control the system clock, memory devices, read and write access, I/O read and write cycles, data bus direction, data and interrupt requests, and speaker driver. The memory devices include hard disks, floppy disks, electrically erasable programmable read-only memory (EEPROM), and random access memory (RAM). The I/O devices include a printer, a modem, and an ethernet communication network.
The personal computer comprises a housing containing a module card rack for holding and interconnecting electronic modules. When the housing is opened, electronic modules are inserted into the rack and connected to a mother board which is located at an end of the computer housing opposite the opening of the housing. The mother board provides the electrical interconnections between modules in the computer including the AT bus, power, and grounds. A user can alter the capability of the personal computer by adding or removing computer modules from the computer housing. For example, memory capacity may be increased by inserting a RAM (Random Access Memory) module into the housing.
Each device connected to the AT bus and having memory must also have a memory base address that defines the memory space that the device uses so that the CPU may command reads from or writes into that memory. It is necessary that each memory have a unique memory base address so that only one device responds to these read and write commands. The AT bus specification allocates certain memory addresses to particular devices. More specifically, the hard disk, the floppy disk drives, and RAM memory are each assigned a unique memory base address ranges. Accordingly, every personal computer uses these addresses for communication with the hard disk, the floppy disk drives, and the RAM. In contrast, when a new device is connected to the personal computer, its memory base address must not be one of the previously allocated addresses but can be any address within an unreserved address range. However, when multiple devices are added, each with its own memory and corresponding memory base address, it is possible that two or more devices may have identical memory base addresses. If this should happen, during the initialization routine at system power up, the CPU sends an address that corresponds to the two or more different devices. Each of the two or more different devices respond to the address command and all try to either read from or write into memory. This multiple response creates a conflict on the data portion of the bus. The CPU in some cases, may be able to detect this conflict on the bus because, for example, during system boot-up and during a read, the data that will be read may differ from system expected values.
In existing systems, one type of add-on card is an Ethernet interface module for interfacing between the AT bus and an Ethernet network system. The requirements of the Ethernet are described in detail in Information Processing Systems--Local Area Networks--Part 3: Carrier sense multiple access with collision detection (CSMA/DC) access method and physical layer specifications, International Standard ISO, 8902-3: 1989, ANSI/IEEE Std 802.3--1988, published by Institute of Electrical and Electronics Engineers, Inc., 1989, the subject matter of which is incorporated herein by reference. Also, in existing systems, when a memory address conflict is detected, it is necessary to power-down the system and remove from the system the add-on card that is suspected of having a conflict, alter its configuration by whatever means that are provided on the module, and then replace it in the system and power up and retest the modules's operation. (The means used in existing systems for altering base addresses are moveable jumpers or switches.) The CPU again executes its initialization routine, and, if another memory base address conflict is detected, the process of removing the module and physically changing its memory base address is repeated, until the memory conflict is eliminated. If no memory conflict is detected, the CPU continues executing its initialization routine.
Several I/O interface devices, connected to the AT bus each have an I/O base address. When the device detects its I/O base address on the bus, the device responds to the commands on the bus. As with the memory base address, it is necessary for each device to have a unique I/O base address. Similar to memory addresses, the AT bus specification allocates I/O address ranges to certain devices. Accordingly, these I/O addresses are used only by these devices. However, when other devices are added to the AT bus, each device must have its own unique I/O address. However, as with the memory base address, these devices do not have preassigned I/O addresses. Thus, the AT bus specification allocates I/O address ranges to the new devices.
However, when a new device is connected to the bus, the system does not know whether two or more devices on the bus are using the same I/O base address until the CPU runs through its initialization routine. Thus, when the CPU sends an I/O bus address to the two or more devices on the bus using the same address, the two or more devices both respond and generate a conflict on the bus.
Existing systems with EEPROM based configuration resolve conflicts in the I/O base address by a method paralleling the method for resolving an address conflict on jumper or switch based designs. In particular, for the Ethernet module with an EEPROM based configuration the user of the computer first powers on the computer. During the CPU initialization routine, when an I/O memory address conflict is detected, the user must remove the module from the first computer and insert it into a second system having no I/O base address conflicts. The user may then alter the I/O address of the module by rewriting the EEPROM. After which, the module now having its original configuration changed may be reinstalled in the original system.
The method for resolving address conflicts is labor intensive, expensive, and subject to operator error. The process requires removing a module from the first computer, inserting it into the second computer, powering it up and reconfiguring it in the second system, removing it from the second system, wires on the module, reinserting it into and retesting it in the first system, and repeating this process until all conflicts are eliminated. These steps each require labor for performing them and are thus time consuming. The added time for set up, test, and rework increase the cost of the module. Further, the multiple steps increase the likelihood of errors during rework and of damaging the module or the computer by repetitively removing and installing the module in the two computer systems.
It is desired to alter the memory and I/O address of an add-on module without jumpers and to automate and reduce the number of steps in the alteration.